Conventional power MOSFETs use a thick (4 to 10 μm) top layer of metalization for connection to the source regions thereof due to the large currents that the metal has to conduct during the operation of the device. Because of the thickness of the top metal, wet etching is used to pattern the same during fabrication. The use of wet etching requires the metal design rules to be large. Therefore, multiple gate buses in a conventional power MOSFET consume a large area of the semiconductor die, which could otherwise be used for the active part of the device.
When a power MOSFET is configured for flip-mounting onto conductive pads using solder or the like additional issues further lead to the inefficient use of semiconductor area. For example, the gate pad required for flip-mounting is large compared with a wire-bonded device, which wastes more semiconductor area that could be used for the active region of the device. In addition, the layout of a large source pad required for flip-mounting may restrict the use of multiple gate buses.